View MB84VD21194A-85-PTS_7119559.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds05-50202-3e fujitsu semiconductor data sheet stac k e d mcp (multi-chip p a c k age) flash memor y & sram cmos 16m ( 8/ 16) flash memory & 4m ( 8/ 16) static ram mb84vd2118xa -85 / mb84vd2119xa -85 n nn n features ? p o wer supp l y v o lt a g e of 2.7 v to 3.6 v ? high performance 85 ns maximum access time ? operating temperature - 25 c to + 85 c ? package 69-ball fbga, 56-pin tsop(i) (contin ued) n nn n product line up *: both v cc f and v cc s must be in recommended operation range when either part is being accessed. n nn n packages flash memory sram ordering part no. v cc f*, v cc s* = 3.0 v mb84vd2118xa-85/mb84vd2119xa-85 max. address access time (ns) 85 85 max. ce access time (ns) 85 85 max. oe access time (ns) 35 45 + 0.6 v - 0.3 v 69-ball plastic fbga 56-pin plastic tsop(i) (bga-69p-m02) (fpt-56p-m04)
mb84vd2118xa -85 /mb84vd2119xa -85 2 (continued) 1. flash memory ? simultaneous read/write operations (dual bank) multiple devices available with different bank sizes (refer to pin description) host system can program or erase in one bank, then immediately and simultaneously read from the other bank zero latency between read and write operations read-while-erase read-while-program ? minimum 100,000 write/erase cycles ? sector erase architecture eight 4 k words and thirty one 32 k words. any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture mb84vd2118xa : top sector mb84vd2119xa : bottom sector ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ? data polling and toggle bit feature for detection of program or erase cycle completion ? ready-busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ? low v cc f write inhibit 2.5 v ? hidden rom (hi-rom) region 64k byte of hi-rom, accessible through a new hi-rom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp /acc input pin at v il , allows protection of boot sectors, regardless of sector protection/unprotection status (mb84vd2118xa : sa37, sa38 mb84vd2119xa : sa0, sa1) at v ih , allows removal of boot sector protection at v acc , program time will reduce by 40%. ? erase suspend / resume suspends the erase operation to allow a read in another sector within the same device ? please refer to mbm29dl16xtd/bd data sheet in detailed function 2. sram ? power dissipation operating : 40 ma max. standby : 7 m a max. ? power down features using ce1 s and ce2s ? data retention supply voltage : 1.5 v to 3.6 v ? ce1s and ce2s chip select ? byte data control : lb s (dq 0 to dq 7 ) , ub s (dq 8 to dq 15 ) *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mb84vd2118xa- 85 /mb84vd2119xa- 85 3 n n n n pin assignments (top view) (bga-69p-m02) 1234567 910 8 a b c d e f g h j k n.c. n.c. n.c. we a 8 a 19 a 9 a 10 dq 6 a 12 a 13 a 14 sa a 16 a 15 n.c. n.c. n.c. n.c. a 11 ce2 s n.c. n.c. n.c. a 7 a 6 a 5 a 4 v ss a 3 a 2 a 1 a 0 cef oe dq 0 dq 10 dq 8 dq 2 v cc fv cc s dq 11 dq 12 dq 13 dq 4 dq 3 dq 9 dq 1 a 17 a 18 ub s reset ry/by dq 7 dq 15 / a - 1 v ss ciof dq 14 dq 5 cio s n.c. n.c. ce1 s n.c. n.c. n.c. n.c. lb s wp/ acc
mb84vd2118xa -85 /mb84vd2119xa -85 4 (top view) (fpt-56p-m04) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 n.c. a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 n.c. we ce2s reset wp/acc ry/by ubs lbs a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 n.c. 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a 16 ciof v ss sa dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 cios v cc s v cc f dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce1s cef a 0
mb84vd2118xa- 85 /mb84vd2119xa- 85 5 n n n n pin description pin name function input/output a 0 to a 17 address inputs (common) i a -1 , a 18 , a 19 address input (flash) i sa address input (sram) i dq 0 to dq 15 data inputs/outputs (common) i/o ce f chip enable (flash) i ce1 s chip enable (sram) i ce2s chip enable (sram) i oe output enable (common) i we write enable (common) i ry/by ready/busy outputs (flash) open drain output o ub s upper byte control (sram) i lb s lower byte control (sram) i ciof i/o configuration (flash) ciof = v cc f is word mode ( 16), ciof = v ss is byte mode ( 8) i cios i/o configuration (sram) cios = v cc s is word mode ( 16), cios = v ss is byte mode ( 8) i reset hardware reset pin/sector protection unlock (flash) i wp /acc write protect / acceleration (flash) i n.c. no internal connection ? v ss device ground (common) power v cc f device power supply (flash) power v cc s device power supply (sram) power
mb84vd2118xa -85 /mb84vd2119xa -85 6 n n n n block diagram v cc fv ss v cc sv ss ry/by a 0 to a 19 a 0 to a 17 a 0 to a 19 a -1 wp/acc reset cef ciof sa lbs ubs we oe ce1s ce2s cios 16 m bit flash memory 4 m bit static ram dq 0 to dq 15 /a -1 dq 0 to dq 15 /a -1 dq 0 to dq 15 /a -1
mb84vd2118xa- 85 /mb84vd2119xa- 85 7 n n n n device bus operations table 2.1 user bus operations (flash = word mode; ciof = v cc f, sram = word mode; cios = v cc s) legend: l = v il , h = v ih , x = v il or v ih . see electrical characteristics 1. dc characteristics for voltage levels. *1: other operations except for indicated this column are inhibited. *2: we can be v il if oe is v il , oe at v ih initiates the write operations. *3: do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. *4: it is also used for the extended sector group protections. *5: wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9v) ; program time will reduce by 40 % . *6: sa; dont care or open. operation * 1, * 3 ce fce1 sce2s oe we sa * 6 lb sub s dq 0 to dq 7 dq 8 to dq 15 reset wp / acc * 5 full standby h hx x x x x x high-z high-z h x xl output disable hl h h h x x x high-z high-z hx x x x h h high-z high-z l hx h h x x x high-z high-z xl read from flash * 2 l hx lh x xx d out d out hx xl write to flash l hx hl x xx d in d in hx xl read from sram h l h l h x ll d out d out hx hlhigh-zd out lh d out high-z write to sram h l h x l x ll d in d in hx hlhigh-z d in lh d in high-z temporary sector group unprotection * 4 xxxxxxxx x x v id x flash hardware reset x hx x x x x x high-z high-z l x xl boot block sector write protection xxxxxxxx x x x l
mb84vd2118xa -85 /mb84vd2119xa -85 8 table 2.2 user bus operations (flash = word mode; ciof = v cc f, sram = byte mode; cios = v ss ) legend: l = v il , h = v ih , x = v il or v ih . see electrical characteristics 1. dc characteristics for voltage levels. *1: other operations except for indicated this column are inhibited. *2: we can be v il if oe is v il , oe at v ih initiates the write operations. *3: do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. *4: it is also used for the extended sector group protections. *5: wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9v) ; program time will reduce by 40%. *6: lb s , ub s ; dont care or open. operation * 1, * 3 ce fce1 sce2s oe we sa lb s * 6 ub s * 6 dq 0 to dq 7 dq 8 to dq 15 reset wp / acc * 5 full standby h hx x x x x x high-z high-z h x xl output disable hl h h h x x x high-z high-z hx x x x h h high-z high-z l hx h h x x x high-z high-z xl read from flash * 2 l hx lhx x x d out d out hx xl write to flash l hx hlx x x d in d in hx xl read from sram h l h l h sa x x d out high-z h x write to sram h l h x l sa x x d in high-z h x temporary sector group unprotection * 4 xx xxxx x x x x v id x flash hardware reset x hx x x x x x high-z high-z l x xl boot block sector write protection xx xxxx x x x x x l
mb84vd2118xa- 85 /mb84vd2119xa- 85 9 table 2.3 user bus operations (flash = byte mode; ciof = v ss , sram = byte mode; cios = v ss ) legend: l = v il , h = v ih , x = v il or v ih . see electrical characteristics 1. dc characteristics for voltage levels. *1: other operations except for indicated this column are inhibited. *2: we can be v il if oe is v il , oe at v ih initiates the write operations. *3: do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. *4: it is also used for the extended sector group protections. *5: wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9v) ; program time will reduce by 40%. *6: lb s , ub s ; dont care or open. operation * 1, * 3 ce fce1 sce2s dq 1 / a -1 oe we sa lb s * 6 ub s * 6 dq 0 to dq 7 dq 8 to dq 14 reset wp / acc * 5 full standby h hx x x x x x x high-z high-z h x xl output disable hl h x h h x x x high-z high-z hx x x x x h h high-z high-z l hx a -1 h h x x x high-z high-z xl read from flash * 2 l hx a -1 lhx x x d out xh x xl write to flash l hx a -1 hlx x x d in xh x xl read from sram hl h xlhsax x d out high-z h x write to sram hl h xxlsax x d in high-z h x temporary sector group unprotection * 4 xx x xxxx x x x x v id x flash hardware reset x hx x x x x x x high-z high-z l x xl boot block sector write protection xx x xxxx x x x x x l
mb84vd2118xa -85 /mb84vd2119xa -85 10 n n n n flexible sector-erase architecture on flash memory ? eight 4 k words, and thirty one 32 k words. ? individual-sector, multiple-sector, or bulk-erase capability. mb84vd2118xa sector architecture (top boot block) sa38 : 8kb (4kw) sa37 : 8kb (4kw) sa36 : 8kb (4kw) sa35 : 8kb (4kw) sa34 : 8kb (4kw) sa33 : 8kb (4kw) sa32 : 8kb (4kw) sa31 : 8kb (4kw) sa30 : 64kb (32kw) sa29 : 64kb (32kw) sa28 : 64kb (32kw) sa27 : 64kb (32kw) sa26 : 64kb (32kw) sa25 : 64kb (32kw) sa24 : 64kb (32kw) sa23 : 64kb (32kw) sa22 : 64kb (32kw) sa21 : 64kb (32kw) sa20 : 64kb (32kw) sa19 : 64kb (32kw) sa18 : 64kb (32kw) sa17 : 64kb (32kw) sa16 : 64kb (32kw) sa15 : 64kb (32kw) sa14 : 64kb (32kw) sa13 : 64kb (32kw) sa12 : 64kb (32kw) sa11 : 64kb (32kw) sa10 : 64kb (32kw) sa9 : 64kb (32kw) sa8 : 64kb (32kw) sa7 : 64kb (32kw) sa6 : 64kb (32kw) sa5 : 64kb (32kw) sa4 : 64kb (32kw) sa3 : 64kb (32kw) sa2 : 64kb (32kw) sa1 : 64kb (32kw) sa0 : 64kb (32kw) word mode byte mode 0fffffh 1fffffh 0ff000h 1fe000h 0fe000h 1fc000h 0fd000h 1fa000h 0fc000h 1f8000h 0fb000h 1f6000h 0fa000h 1f4000h 0f9000h 1f2000h 0f8000h 1f0000h 0f0000h 1e0000h 0e8000h 1d0000h 0e0000h 1c0000h 0d8000h 1b0000h 0d0000h 1a0000h 0c8000h 190000h 0c0000h 180000h 0b8000h 170000h 0b0000h 160000h 0a8000h 150000h 0a0000h 140000h 098000h 130000h 090000h 120000h 088000h 110000h 080000h 100000h 078000h 0f0000h 070000h 0e0000h 068000h 0d0000h 060000h 0c0000h 058000h 0b0000h 050000h 0a0000h 048000h 090000h 040000h 080000h 038000h 070000h 030000h 060000h 028000h 050000h 020000h 040000h 018000h 030000h 010000h 020000h 008000h 010000h 000000h 000000h bank 1 mb84vd21181a bank 2 mb84vd21181a bank 1 mb84vd21182a bank 1 mb84vd21183a bank 1 mb84vd21184a bank 2 mb84vd21182a bank 2 mb84vd21183a bank 2 mb84vd21184a
mb84vd2118xa- 85 /mb84vd2119xa- 85 11 ? eight 4 k words, and thirty one 32 k words. ? individual-sector, multiple-sector, or bulk-erase capability. mb84vd2119xa sector architecture (bottom boot block) sa38 : 64kb (32kw) sa37 : 64kb (32kw) sa36 : 64kb (32kw) sa35 : 64kb (32kw) sa34 : 64kb (32kw) sa33 : 64kb (32kw) sa32 : 64kb (32kw) sa31 : 64kb (32kw) sa30 : 64kb (32kw) sa29 : 64kb (32kw) sa28 : 64kb (32kw) sa27 : 64kb (32kw) sa26 : 64kb (32kw) sa25 : 64kb (32kw) sa24 : 64kb (32kw) sa23 : 64kb (32kw) sa22 : 64kb (32kw) sa21 : 64kb (32kw) sa20 : 64kb (32kw) sa19 : 64kb (32kw) sa18 : 64kb (32kw) sa17 : 64kb (32kw) sa16 : 64kb (32kw) sa15 : 64kb (32kw) sa14 : 64kb (32kw) sa13 : 64kb (32kw) sa12 : 64kb (32kw) sa11 : 64kb (32kw) sa10 : 64kb (32kw) sa9 : 64kb (32kw) sa8 : 64kb (32kw) sa7 : 8kb (4kw) sa6 : 8kb (4kw) sa5 : 8kb (4kw) sa4 : 8kb (4kw) sa3 : 8kb (4kw) sa2 : 8kb (4kw) sa1 : 8kb (4kw) sa0 : 8kb (4kw) word mode byte mode 0fffffh 1fffffh 0f8000h 1f0000h 0f0000h 1e0000h 0e8000h 1d0000h 0e0000h 1c0000h 0d8000h 1b0000h 0d0000h 1a0000h 0c8000h 190000h 0c0000h 180000h 0b8000h 170000h 0b0000h 160000h 0a8000h 150000h 0a0000h 140000h 098000h 130000h 090000h 120000h 088000h 110000h 080000h 100000h 078000h 0f0000h 070000h 0e0000h 068000h 0d0000h 060000h 0c0000h 058000h 0b0000h 050000h 0a0000h 048000h 090000h 040000h 080000h 038000h 070000h 030000h 060000h 028000h 050000h 020000h 040000h 018000h 030000h 010000h 020000h 008000h 010000h 007000h 00e000h 006000h 00c000h 005000h 00a000h 004000h 008000h 003000h 006000h 002000h 004000h 001000h 002000h 000000h 000000h bank 2 mb84vd21194a bank 2 mb84vd21193a bank 2 mb84vd21192a bank 2 mb84vd21191a bank 1 mb84vd21194a bank 1 mb84vd21193a bank 1 mb84vd21192a bank 1 mb84vd21191a
mb84vd2118xa -85 /mb84vd2119xa -85 12 table 3.1 sector address tables (mb84vd21181) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 00000xxx 000000h to 00ffffh 000000h to 007fffh sa1 00001xxx 010000h to 01ffffh 008000h to 00ffffh sa2 00010xxx 020000h to 02ffffh 010000h to 017fffh sa3 00011xxx 030000h to 03ffffh 018000h to 01ffffh sa4 00100xxx 040000h to 04ffffh 020000h to 027fffh sa5 00101xxx 050000h to 05ffffh 028000h to 02ffffh sa6 00110xxx 060000h to 06ffffh 030000h to 037fffh sa7 00111xxx 070000h to 07ffffh 038000h to 03ffffh sa8 01000xxx 080000h to 08ffffh 040000h to 047fffh sa9 01001xxx 090000h to 09ffffh 048000h to 04ffffh sa10 01010xxx0a0000h to 0a ffffh 050000h to 057fffh sa11 01011xxx0b0000h to 0b ffffh 058000h to 05ffffh sa12 01100xxx0c0000h to 0c ffffh 060000h to 067fffh sa13 01101xxx0d0000h to 0d ffffh 068000h to 06ffffh sa14 01110xxx0e0000h to 0e ffffh 070000h to 077fffh sa15 01111xxx0f0000h to 0ff fffh 078000h to 07ffffh sa16 10000xxx 100000h to 10ffffh 080000h to 087fffh sa17 10001xxx 110000h to 11ffffh 088000h to 08ffffh sa18 10010xxx 120000h to 12ffffh 090000h to 097fffh sa19 10011xxx 130000h to 13ffffh 098000h to 09ffffh sa20 10100xxx 140000h to 14ffffh 0a0000h to 0a7fffh sa21 10101xxx 150000h to 15ffffh 0a8000h to 0affffh sa22 10110xxx 160000h to 16ffffh 0b0000h to 0b7fffh sa23 10111xxx 170000h to 17ffffh 0b8000h to 0bffffh sa24 11000xxx 180000h to 18ffffh 0c0000h to 0c7fffh sa25 11001xxx 190000h to 19ffffh 0c8000h to 0cffffh sa26 11010xxx1a0000h to 1a ffffh 0d0000h to 0d7fffh sa27 11011xxx1b0000h to 1b ffffh 0d8000h to 0dffffh sa28 11100xxx1c0000h to 1c ffffh 0e0000h to 0e7fffh sa29 11101xxx1d0000h to 1d ffffh 0e8000h to 0effffh sa30 11110xxx1e0000h to 1e ffffh 0f0000h to 0f7fffh bank 1 sa31 111110001f0 000h to 1f1fffh 0f8000h to 0f8fffh sa32 111110011f2 000h to 1f3fffh 0f9000h to 0f9fffh sa33 111110101f4 000h to 1f5fffh 0fa000h to 0fafffh sa34 111110111f6 000h to 1f7fffh 0fb000h to 0fbfffh sa35 111111001f8 000h to 1f9fffh 0fc000h to 0fcfffh sa36 111111011fa 000h to 1fbfffh 0fd000h to 0fdfffh sa37 111111101fc 000h to 1fdfffh 0fe000h to 0fefffh sa38 111111111fe000h to 1 fffffh 0ff000h to 0fffffh
mb84vd2118xa- 85 /mb84vd2119xa- 85 13 table 3.2 sector address tables (mb84vd21191) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa0 00000000000 000h to 001fffh 000000h to 000fffh sa1 00000001002 000h to 003fffh 001000h to 001fffh sa2 00000010004 000h to 005fffh 002000h to 002fffh sa3 00000011006 000h to 007fffh 003000h to 003fffh sa4 00000100008 000h to 009fffh 004000h to 004fffh sa5 0000010100a 000h to 00bfffh 005000h to 005fffh sa6 0000011000c 000h to 00dfffh 006000h to 006fffh sa7 0000011100e000h to 00ffffh 007000h to 007fffh bank 2 sa8 00001xxx 010000h to 01ffffh 008000h to 00ffffh sa9 00010xxx 020000h to 02ffffh 010000h to 017fffh sa10 00011xxx 030000h to 03ffffh 018000h to 01ffffh sa11 00100xxx 040000h to 04ffffh 020000h to 027fffh sa12 00101xxx 050000h to 05ffffh 028000h to 02ffffh sa13 00110xxx 060000h to 06ffffh 030000h to 037fffh sa14 00111xxx 070000h to 07ffffh 038000h to 03ffffh sa15 01000xxx 080000h to 08ffffh 040000h to 047fffh sa16 01001xxx 090000h to 09ffffh 048000h to 04ffffh sa17 01010xxx0a0000h to 0a ffffh 050000h to 057fffh sa18 01011xxx0b0000h to 0b ffffh 058000h to 05ffffh sa19 01100xxx0c0000h to 0c ffffh 060000h to 067fffh sa20 01101xxx0d0000h to 0d ffffh 068000h to 06ffffh sa21 01110xxx0e0000h to 0e ffffh 070000h to 077fffh sa22 01111xxx0f0000h to 0ff fffh 078000h to 07ffffh sa23 10000xxx 100000h to 10ffffh 080000h to 087fffh sa24 10001xxx 110000h to 11ffffh 088000h to 08ffffh sa25 10010xxx 120000h to 12ffffh 090000h to 097fffh sa26 10011xxx 130000h to 13ffffh 098000h to 09ffffh sa27 10100xxx 140000h to 14ffffh 0a0000h to 0a7fffh sa28 10101xxx 150000h to 15ffffh 0a8000h to 0affffh sa29 10110xxx 160000h to 16ffffh 0b0000h to 0b7fffh sa30 10111xxx 170000h to 17ffffh 0b8000h to 0bffffh sa31 11000xxx 180000h to 18ffffh 0c0000h to 0c7fffh sa32 11001xxx 190000h to 19ffffh 0c8000h to 0cffffh sa33 11010xxx1a0000h to 1a ffffh 0d0000h to 0d7fffh sa34 11011xxx1b0000h to 1b ffffh 0d8000h to 0dffffh sa35 11100xxx1c0000h to 1c ffffh 0e0000h to 0e7fffh sa36 11101xxx1d0000h to 1d ffffh 0e8000h to 0effffh sa37 11110xxx1e0000h to 1e ffffh 0f0000h to 0f7fffh sa38 11111xxx1f0000h to 1ff fffh 0f8000h to 0fffffh
mb84vd2118xa -85 /mb84vd2119xa -85 14 table 3.3 sector address tables (mb84vd21182) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 00000xxx 000000h to 00ffffh 000000h to 007fffh sa1 00001xxx 010000h to 01ffffh 008000h to 00ffffh sa2 00010xxx 020000h to 02ffffh 010000h to 017fffh sa3 00011xxx 030000h to 03ffffh 018000h to 01ffffh sa4 00100xxx 040000h to 04ffffh 020000h to 027fffh sa5 00101xxx 050000h to 05ffffh 028000h to 02ffffh sa6 00110xxx 060000h to 06ffffh 030000h to 037fffh sa7 00111xxx 070000h to 07ffffh 038000h to 03ffffh sa8 01000xxx 080000h to 08ffffh 040000h to 047fffh sa9 01001xxx 090000h to 09ffffh 048000h to 04ffffh sa10 01010xxx0a0000h to 0a ffffh 050000h to 057fffh sa11 01011xxx0b0000h to 0b ffffh 058000h to 05ffffh sa12 01100xxx0c0000h to 0c ffffh 060000h to 067fffh sa13 01101xxx0d0000h to 0d ffffh 068000h to 06ffffh sa14 01110xxx0e0000h to 0e ffffh 070000h to 077fffh sa15 01111xxx0f0000h to 0ff fffh 078000h to 07ffffh sa16 10000xxx 100000h to 10ffffh 080000h to 087fffh sa17 10001xxx 110000h to 11ffffh 088000h to 08ffffh sa18 10010xxx 120000h to 12ffffh 090000h to 097fffh sa19 10011xxx 130000h to 13ffffh 098000h to 09ffffh sa20 10100xxx 140000h to 14ffffh 0a0000h to 0a7fffh sa21 10101xxx 150000h to 15ffffh 0a8000h to 0affffh sa22 10110xxx 160000h to 16ffffh 0b0000h to 0b7fffh sa23 10111xxx 170000h to 17ffffh 0b8000h to 0bffffh sa24 11000xxx 180000h to 18ffffh 0c0000h to 0c7fffh sa25 11001xxx 190000h to 19ffffh 0c8000h to 0cffffh sa26 11010xxx1a0000h to 1a ffffh 0d0000h to 0d7fffh sa27 11011xxx1b0000h to 1b ffffh 0d8000h to 0dffffh bank 1 sa28 11100xxx1c0000h to 1c ffffh 0e0000h to 0e7fffh sa29 11101xxx1d0000h to 1d ffffh 0e8000h to 0effffh sa30 11110xxx1e0000h to 1e ffffh 0f0000h to 0f7fffh sa31 111110001f0 000h to 1f1fffh 0f8000h to 0f8fffh sa32 111110011f2 000h to 1f3fffh 0f9000h to 0f9fffh sa33 111110101f4 000h to 1f5fffh 0fa000h to 0fafffh sa34 111110111f6 000h to 1f7fffh 0fb000h to 0fbfffh sa35 111111001f8 000h to 1f9fffh 0fc000h to 0fcfffh sa36 111111011fa 000h to 1fbfffh 0fd000h to 0fdfffh sa37 111111101fc 000h to 1fdfffh 0fe000h to 0fefffh sa38 111111111fe000h to 1 fffffh 0ff000h to 0fffffh
mb84vd2118xa- 85 /mb84vd2119xa- 85 15 table 3.4 sector address tables (mb84vd21192) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa0 00000000000 000h to 001fffh 000000h to 000fffh sa1 00000001002 000h to 003fffh 001000h to 001fffh sa2 00000010004 000h to 005fffh 002000h to 002fffh sa3 00000011006 000h to 007fffh 003000h to 003fffh sa4 00000100008 000h to 009fffh 004000h to 004fffh sa5 0000010100a 000h to 00bfffh 005000h to 005fffh sa6 0000011000c 000h to 00dfffh 006000h to 006fffh sa7 0000011100e000h to 00ffffh 007000h to 007fffh sa8 00001xxx 010000h to 01ffffh 008000h to 00ffffh sa9 00010xxx 020000h to 02ffffh 010000h to 017fffh sa10 00011xxx 030000h to 03ffffh 018000h to 01ffffh bank 2 sa11 00100xxx 040000h to 04ffffh 020000h to 027fffh sa12 00101xxx 050000h to 05ffffh 028000h to 02ffffh sa13 00110xxx 060000h to 06ffffh 030000h to 037fffh sa14 00111xxx 070000h to 07ffffh 038000h to 03ffffh sa15 01000xxx 080000h to 08ffffh 040000h to 047fffh sa16 01001xxx 090000h to 09ffffh 048000h to 04ffffh sa17 01010xxx0a0000h to 0a ffffh 050000h to 057fffh sa18 01011xxx0b0000h to 0b ffffh 058000h to 05ffffh sa19 01100xxx0c0000h to 0c ffffh 060000h to 067fffh sa20 01101xxx0d0000h to 0d ffffh 068000h to 06ffffh sa21 01110xxx0e0000h to 0e ffffh 070000h to 077fffh sa22 01111xxx0f0000h to 0ff fffh 078000h to 07ffffh sa23 10000xxx 100000h to 10ffffh 080000h to 087fffh sa24 10001xxx 110000h to 11ffffh 088000h to 08ffffh sa25 10010xxx 120000h to 12ffffh 090000h to 097fffh sa26 10011xxx 130000h to 13ffffh 098000h to 09ffffh sa27 10100xxx 140000h to 14ffffh 0a0000h to 0a7fffh sa28 10101xxx 150000h to 15ffffh 0a8000h to 0affffh sa29 10110xxx 160000h to 16ffffh 0b0000h to 0b7fffh sa30 10111xxx 170000h to 17ffffh 0b8000h to 0bffffh sa31 11000xxx 180000h to 18ffffh 0c0000h to 0c7fffh sa32 11001xxx 190000h to 19ffffh 0c8000h to 0cffffh sa33 11010xxx1a0000h to 1a ffffh 0d0000h to 0d7fffh sa34 11011xxx1b0000h to 1b ffffh 0d8000h to 0dffffh sa35 11100xxx1c0000h to 1c ffffh 0e0000h to 0e7fffh sa36 11101xxx1d0000h to 1d ffffh 0e8000h to 0effffh sa37 11110xxx1e0000h to 1e ffffh 0f0000h to 0f7fffh sa38 11111xxx1f0000h to 1ff fffh 0f8000h to 0fffffh
mb84vd2118xa -85 /mb84vd2119xa -85 16 table 3.5 sector address tables (mb84vd21183) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 00000xxx 000000h to 00ffffh 000000h to 007fffh sa1 00001xxx 010000h to 01ffffh 008000h to 00ffffh sa2 00010xxx 020000h to 02ffffh 010000h to 017fffh sa3 00011xxx 030000h to 03ffffh 018000h to 01ffffh sa4 00100xxx 040000h to 04ffffh 020000h to 027fffh sa5 00101xxx 050000h to 05ffffh 028000h to 02ffffh sa6 00110xxx 060000h to 06ffffh 030000h to 037fffh sa7 00111xxx 070000h to 07ffffh 038000h to 03ffffh sa8 01000xxx 080000h to 08ffffh 040000h to 047fffh sa9 01001xxx 090000h to 09ffffh 048000h to 04ffffh sa10 01010xxx0a0000h to 0a ffffh 050000h to 057fffh sa11 01011xxx0b0000h to 0b ffffh 058000h to 05ffffh sa12 01100xxx0c0000h to 0c ffffh 060000h to 067fffh sa13 01101xxx0d0000h to 0d ffffh 068000h to 06ffffh sa14 01110xxx0e0000h to 0e ffffh 070000h to 077fffh sa15 01111xxx0f0000h to 0ff fffh 078000h to 07ffffh sa16 10000xxx 100000h to 10ffffh 080000h to 087fffh sa17 10001xxx 110000h to 11ffffh 088000h to 08ffffh sa18 10010xxx 120000h to 12ffffh 090000h to 097fffh sa19 10011xxx 130000h to 13ffffh 098000h to 09ffffh sa20 10100xxx 140000h to 14ffffh 0a0000h to 0a7fffh sa21 10101xxx 150000h to 15ffffh 0a8000h to 0affffh sa22 10110xxx 160000h to 16ffffh 0b0000h to 0b7fffh sa23 10111xxx 170000h to 17ffffh 0b8000h to 0bffffh bank 1 sa24 11000xxx 180000h to 18ffffh 0c0000h to 0c7fffh sa25 11001xxx 190000h to 19ffffh 0c8000h to 0cffffh sa26 11010xxx1a0000h to 1a ffffh 0d0000h to 0d7fffh sa27 11011xxx1b0000h to 1b ffffh 0d8000h to 0dffffh sa28 11100xxx1c0000h to 1c ffffh 0e0000h to 0e7fffh sa29 11101xxx1d0000h to 1d ffffh 0e8000h to 0effffh sa30 11110xxx1e0000h to 1e ffffh 0f0000h to 0f7fffh sa31 111110001f0 000h to 1f1fffh 0f8000h to 0f8fffh sa32 111110011f2 000h to 1f3fffh 0f9000h to 0f9fffh sa33 111110101f4 000h to 1f5fffh 0fa000h to 0fafffh sa34 111110111f6 000h to 1f7fffh 0fb000h to 0fbfffh sa35 111111001f8 000h to 1f9fffh 0fc000h to 0fcfffh sa36 111111011fa 000h to 1fbfffh 0fd000h to 0fdfffh sa37 111111101fc 000h to 1fdfffh 0fe000h to 0fefffh sa38 111111111fe000h to 1 fffffh 0ff000h to 0fffffh
mb84vd2118xa- 85 /mb84vd2119xa- 85 17 table 3.6 sector address tables (mb84vd21193) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa0 00000000000 000h to 001fffh 000000h to 000fffh sa1 00000001002 000h to 003fffh 001000h to 001fffh sa2 00000010004 000h to 005fffh 002000h to 002fffh sa3 00000011006 000h to 007fffh 003000h to 003fffh sa4 00000100008 000h to 009fffh 004000h to 004fffh sa5 0000010100a 000h to 00bfffh 005000h to 005fffh sa6 0000011000c 000h to 00dfffh 006000h to 006fffh sa7 0000011100e000h to 00ffffh 007000h to 007fffh sa8 00001xxx 010000h to 01ffffh 008000h to 00ffffh sa9 00010xxx 020000h to 02ffffh 010000h to 017fffh sa10 00011xxx 030000h to 03ffffh 018000h to 01ffffh sa11 00100xxx 040000h to 04ffffh 020000h to 027fffh sa12 00101xxx 050000h to 05ffffh 028000h to 02ffffh sa13 00110xxx 060000h to 06ffffh 030000h to 037fffh sa14 00111xxx 070000h to 07ffffh 038000h to 03ffffh bank 2 sa15 01000xxx 080000h to 08ffffh 040000h to 047fffh sa16 01001xxx 090000h to 09ffffh 048000h to 04ffffh sa17 01010xxx0a0000h to 0a ffffh 050000h to 057fffh sa18 01011xxx0b0000h to 0b ffffh 058000h to 05ffffh sa19 01100xxx0c0000h to 0c ffffh 060000h to 067fffh sa20 01101xxx0d0000h to 0d ffffh 068000h to 06ffffh sa21 01110xxx0e0000h to 0e ffffh 070000h to 077fffh sa22 01111xxx0f0000h to 0ff fffh 078000h to 07ffffh sa23 10000xxx 100000h to 10ffffh 080000h to 087fffh sa24 10001xxx 110000h to 11ffffh 088000h to 08ffffh sa25 10010xxx 120000h to 12ffffh 090000h to 097fffh sa26 10011xxx 130000h to 13ffffh 098000h to 09ffffh sa27 10100xxx 140000h to 14ffffh 0a0000h to 0a7fffh sa28 10101xxx 150000h to 15ffffh 0a8000h to 0affffh sa29 10110xxx 160000h to 16ffffh 0b0000h to 0b7fffh sa30 10111xxx 170000h to 17ffffh 0b8000h to 0bffffh sa31 11000xxx 180000h to 18ffffh 0c0000h to 0c7fffh sa32 11001xxx 190000h to 19ffffh 0c8000h to 0cffffh sa33 11010xxx1a0000h to 1a ffffh 0d0000h to 0d7fffh sa34 11011xxx1b0000h to 1b ffffh 0d8000h to 0dffffh sa35 11100xxx1c0000h to 1c ffffh 0e0000h to 0e7fffh sa36 11101xxx1d0000h to 1d ffffh 0e8000h to 0effffh sa37 11110xxx1e0000h to 1e ffffh 0f0000h to 0f7fffh sa38 11111xxx1f0000h to 1ff fffh 0f8000h to 0fffffh
mb84vd2118xa -85 /mb84vd2119xa -85 18 table 3.7 sector address tables (mb84vd21184) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 00000xxx 000000h to 00ffffh 000000h to 007fffh sa1 00001xxx 010000h to 01ffffh 008000h to 00ffffh sa2 00010xxx 020000h to 02ffffh 010000h to 017fffh sa3 00011xxx 030000h to 03ffffh 018000h to 01ffffh sa4 00100xxx 040000h to 04ffffh 020000h to 027fffh sa5 00101xxx 050000h to 05ffffh 028000h to 02ffffh sa6 00110xxx 060000h to 06ffffh 030000h to 037fffh sa7 00111xxx 070000h to 07ffffh 038000h to 03ffffh sa8 01000xxx 080000h to 08ffffh 040000h to 047fffh sa9 01001xxx 090000h to 09ffffh 048000h to 04ffffh sa10 01010xxx0a0000h to 0a ffffh 050000h to 057fffh sa11 01011xxx0b0000h to 0b ffffh 058000h to 05ffffh sa12 01100xxx0c0000h to 0c ffffh 060000h to 067fffh sa13 01101xxx0d0000h to 0d ffffh 068000h to 06ffffh sa14 01110xxx0e0000h to 0e ffffh 070000h to 077fffh sa15 01111xxx0f0000h to 0ff fffh 078000h to 07ffffh bank 1 sa16 10000xxx 100000h to 10ffffh 080000h to 087fffh sa17 10001xxx 110000h to 11ffffh 088000h to 08ffffh sa18 10010xxx 120000h to 12ffffh 090000h to 097fffh sa19 10011xxx 130000h to 13ffffh 098000h to 09ffffh sa20 10100xxx 140000h to 14ffffh 0a0000h to 0a7fffh sa21 10101xxx 150000h to 15ffffh 0a8000h to 0affffh sa22 10110xxx 160000h to 16ffffh 0b0000h to 0b7fffh sa23 10111xxx 170000h to 17ffffh 0b8000h to 0bffffh sa24 11000xxx 180000h to 18ffffh 0c0000h to 0c7fffh sa25 11001xxx 190000h to 19ffffh 0c8000h to 0cffffh sa26 11010xxx1a0000h to 1a ffffh 0d0000h to 0d7fffh sa27 11011xxx1b0000h to 1b ffffh 0d8000h to 0dffffh sa28 11100xxx1c0000h to 1c ffffh 0e0000h to 0e7fffh sa29 11101xxx1d0000h to 1d ffffh 0e8000h to 0effffh sa30 11110xxx1e0000h to 1e ffffh 0f0000h to 0f7fffh sa31 111110001f0 000h to 1f1fffh 0f8000h to 0f8fffh sa32 111110011f2 000h to 1f3fffh 0f9000h to 0f9fffh sa33 111110101f4 000h to 1f5fffh 0fa000h to 0fafffh sa34 111110111f6 000h to 1f7fffh 0fb000h to 0fbfffh sa35 111111001f8 000h to 1f9fffh 0fc000h to 0fcfffh sa36 111111011fa 000h to 1fbfffh 0fd000h to 0fdfffh sa37 111111101fc 000h to 1fdfffh 0fe000h to 0fefffh sa38 111111111fe000h to 1 fffffh 0ff000h to 0fffffh
mb84vd2118xa- 85 /mb84vd2119xa- 85 19 table 3.8 sector address tables (mb84vd21194) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa0 00000000000 000h to 001fffh 000000h to 000fffh sa1 00000001002 000h to 003fffh 001000h to 001fffh sa2 00000010004 000h to 005fffh 002000h to 002fffh sa3 00000011006 000h to 007fffh 003000h to 003fffh sa4 00000100008 000h to 009fffh 004000h to 004fffh sa5 0000010100a 000h to 00bfffh 005000h to 005fffh sa6 0000011000c 000h to 00dfffh 006000h to 006fffh sa7 0000011100e000h to 00ffffh 007000h to 007fffh sa8 00001xxx 010000h to 01ffffh 008000h to 00ffffh sa9 00010xxx 020000h to 02ffffh 010000h to 017fffh sa10 00011xxx 030000h to 03ffffh 018000h to 01ffffh sa11 00100xxx 040000h to 04ffffh 020000h to 027fffh sa12 00101xxx 050000h to 05ffffh 028000h to 02ffffh sa13 00110xxx 060000h to 06ffffh 030000h to 037fffh sa14 00111xxx 070000h to 07ffffh 038000h to 03ffffh sa15 01000xxx 080000h to 08ffffh 040000h to 047fffh sa16 01001xxx 090000h to 09ffffh 048000h to 04ffffh sa17 01010xxx0a0000h to 0a ffffh 050000h to 057fffh sa18 01011xxx0b0000h to 0b ffffh 058000h to 05ffffh sa19 01100xxx0c0000h to 0c ffffh 060000h to 067fffh sa20 01101xxx0d0000h to 0d ffffh 068000h to 06ffffh sa21 01110xxx0e0000h to 0e ffffh 070000h to 077fffh sa22 01111xxx0f0000h to 0ff fffh 078000h to 07ffffh bank 2 sa23 10000xxx 100000h to 10ffffh 080000h to 087fffh sa24 10001xxx 110000h to 11ffffh 088000h to 08ffffh sa25 10010xxx 120000h to 12ffffh 090000h to 097fffh sa26 10011xxx 130000h to 13ffffh 098000h to 09ffffh sa27 10100xxx 140000h to 14ffffh 0a0000h to 0a7fffh sa28 10101xxx 150000h to 15ffffh 0a8000h to 0affffh sa29 10110xxx 160000h to 16ffffh 0b0000h to 0b7fffh sa30 10111xxx 170000h to 17ffffh 0b8000h to 0bffffh sa31 11000xxx 180000h to 18ffffh 0c0000h to 0c7fffh sa32 11001xxx 190000h to 19ffffh 0c8000h to 0cffffh sa33 11010xxx1a0000h to 1a ffffh 0d0000h to 0d7fffh sa34 11011xxx1b0000h to 1b ffffh 0d8000h to 0dffffh sa35 11100xxx1c0000h to 1c ffffh 0e0000h to 0e7fffh sa36 11101xxx1d0000h to 1d ffffh 0e8000h to 0effffh sa37 11110xxx1e0000h to 1e ffffh 0f0000h to 0f7fffh sa38 11111xxx1f0000h to 1ff fffh 0f8000h to 0fffffh
mb84vd2118xa -85 /mb84vd2119xa -85 20 table 4.1 sector group address (mb84vd2118xa) (top boot block) sector group a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000xxx sa0 sga1 00001xxx sa1 to sa3 00010xxx 00011xxx sga2 0 0 1xxxxxsa4 to sa7 sga3 0 1 0 x x x x x sa8 to sa11 sga4 0 1 1 x x x x x sa12 to sa15 sga5 1 0 0 x x x x x sa16 to sa19 sga6 1 0 1 x x x x x sa20 to sa23 sga7 1 1 0 x x x x x sa24 to sa27 sga8 11100xxx sa28 to sa30 11101xxx 11110xxx sga9 11111000 sa31 sga1011111001 sa32 sga1111111010 sa33 sga1211111011 sa34 sga1311111100 sa35 sga1411111101 sa36 sga1511111110 sa37 sga1611111111 sa38
mb84vd2118xa- 85 /mb84vd2119xa- 85 21 table 4.2 sector group address (mb84vd2119xa) (bottom boot block) sector group a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000000 sa0 sga1 00000001 sa1 sga2 00000010 sa2 sga3 00000011 sa3 sga4 00000100 sa4 sga5 00000101 sa5 sga6 00000110 sa6 sga7 00000111 sa7 sga8 00001xxx sa8 to sa10 00010xxx 00011xxx sga9 0 0 1 x x x x x sa11 to sa14 sga10 0 1 0 x x x x x sa15 to sa18 sga11 0 1 1 x x x x x sa19 to sa22 sga12 1 0 0 x x x x x sa23 to sa26 sga13 1 0 1 x x x x x sa27 to sa30 sga14 1 1 0 x x x x x sa31 to sa34 sga15 11100xxx sa35 to sa37 11101xxx 11110xxx sga16 1 1 1 1 1 x x x sa38
mb84vd2118xa -85 /mb84vd2119xa -85 22 table 5 flash memory autoselect codes *1 : a -1 is for byte mode. *2 : output 01h at protected sector address and output 00h at unprotected sector address. type a 12 to a 19 a 6 a 1 a 0 a -1 * 1 code (hex) manufacturers code x v il v il v il v il 04h device code mb84vd21181a byte xv il v il v ih v il 36h word x 2236h mb84vd21191a byte xv il v il v ih v il 39h word x 2239h mb84vd21182a byte xv il v il v ih v il 2dh word x 222dh mb84vd21192a byte xv il v il v ih v il 2eh word x 222eh mb84vd21183a byte xv il v il v ih v il 28h word x 2228h mb84vd21193a byte xv il v il v ih v il 2bh word x 222bh mb84vd21184a byte xv il v il v ih v il 33h word x 2233h mb84vd21194a byte xv il v il v ih v il 35h word x 2235h sector group protect sector group address v il v ih v il v il 01h* 2
mb84vd2118xa- 85 /mb84vd2119xa- 85 23 table 6 flash memory command definitions command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset * 1 1 xxxh f0h ? ? ? ??????? read/reset * 1 word 3 555h aah 2aah 55h 555h f0h ra rd ???? byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h ?????? byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0h pa pd ???? byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h sector erase suspend 1 ba b0h ? ? ? ??????? sector erase resume 1 ba 30h ? ? ? ??????? set to fast mode word 3 555h aah 2aah 55h 555h 20h ?????? byte aaah 555h aaah fast program * 2 word 2 xxxh a0h pa pd ? ??????? byte reset from fast mode * 2 word 2 ba 90h xxxh f0h * 6 ? ??????? byte extended sector group protection * 3 word 4 xxxh 60h spa 60h spa 40h spa sd ???? byte query * 4 word 1 55h 98h ? ? ? ??????? byte aah hi-rom entry word 3 555h aah 2aah 55h 555h 88h ?????? byte aaah 555h aaah hi-rom program * 5 word 4 555h aah 2aah 55h 555h a0h pa pd ???? byte aaah 555h aaah hi-rom erase * 5 word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h hra 30h byte aaah 555h aaah aaah 555h hi-rom exit * 5 word 4 555h aah 2aah 55h (hrba) 555h 90h xxxh 00h ???? byte aaah 555h (hrba) aaah
mb84vd2118xa -85 /mb84vd2119xa -85 24 *1: both read/reset commands are functionally equivalent, resetting the device to the read mode. *2: this command is valid while fast mode. *3: this command is valid while reset = v id . *4: the valid address is a 0 to a 6 . *5: this command is valid while hi-rom mode. *6: the data 00h is also acceptable. address bits a 12 to a 19 = x = h or l for all address commands except for program address (pa) , sector address (sa) , and bank address (ba) . bus operations are defined in table 2 user bus operations. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 15 to a 19 ) spa = sector group address to be protected. set sector group address (sga) and (a 6 , a 1 , a 0 ) = (0, 1, 0). hra = address of the hidden-rom area. spa = sector group address to be protected. set sector group address (sga) and (a 6 , a 1 , a 0 ) = (0, 1, 0). hra = address of the hidden-rom area. mb84vd2118xa (top boot type) word mode: 0f8000h to 0fffffh byte mode: 1f0000h to 1fffffh mb84vd2119xa (bottom boot type) word mode: 000000h to 007fffh byte mode: 000000h to 00ffffh hrba = bank addrss of the hidden-rom area. mb84vd2118xa (top boot type) : a 15 = a 16 = a 17 = a 18 = a 19 = a 20 = 1 mb84vd2119xa (bottom boot type) : a 15 = a 16 = a 17 = a 18 = a 19 = a 20 = 0 rd = data read from location ra during read operation. pd = data to be programmed at location pa. sd = sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. the system should generate the following address patterns; word mode : 555h or 2aah to addresses a 0 to a 10 byte mode : aaah or 555h to addresses a -1 and a 0 to a 10
mb84vd2118xa- 85 /mb84vd2119xa- 85 25 n n n n absolute maximum ratings *1: minimum dc voltage on input or i/o pins is C0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f +0.4 v or v cc s+0.4 v. during voltage transitions, input or i/o pins may overshoot to v cc f+2.0 v or v cc s+2.0 v for periods of up to 20 ns. *2: minimum dc input voltage on reset pin is C0.5 v. during voltage transitions, reset pin may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (vin-v cc f or v cc s) does not exceed 9.0 v. maximum dc input voltage on reset pin is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. *3: minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may undershoot vss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0 v for periods of up to 20 ns, when v cc f is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions note: operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 25 + 85 c voltage with respect to ground all pins except reset and wp /acc * 1 v in , v out - 0.3 v cc f + 0.4 v v cc s + 0.4 v cc f/v cc s supply * 1 v cc f, v cc s - 0.3 + 4.0 v reset * 2 v in - 0.5 + 13.0 v wp /acc * 3 v in - 0.5 + 10.5 v parameter symbol value unit min. max. ambient temperature t a - 25 + 85 c v cc f/v cc s supply voltages v cc f, v cc s + 2.7 + 3.6 v
mb84vd2118xa -85 /mb84vd2119xa -85 26 n n n n electrical characteristics 1. dc characteristics (continued) parameter symbol test conditions value unit min. typ. max. input leakage current i li v in = v ss to v cc f, v cc s - 1.0 ?+ 1.0 m a output leakage current i lo v out = v ss to v cc f, v cc s - 1.0 ?+ 1.0 m a reset inputs leakage current i lit v cc f = v cc f max, reset = 12.5v ?? 35 m a acc input leakage current i lia v cc f = v cc f max, wp /acc = v acc max ?? 20 ma flash v cc active current (read) * 1 i cc1 f ce f = v il , oe = v ih t cycle = 5 mhz byte ?? 13 ma t cycle = 5 mhz word ?? 15 t cycle = 1 mhz byte ?? 7 ma t cycle = 1 mhz word ?? 7 flash v cc active current (program/erase) * 2 i cc2 fce f = v il , oe = v ih ?? 35 ma flash v cc active current (read-while-program) * 5 i cc3 fce f = v il , oe = v ih byte ?? 48 ma word ?? 50 flash v cc active current (read-while-erase) * 5 i cc4 fce f = v il , oe = v ih byte ?? 48 ma word ?? 50 flash v cc active current (erase-suspend-pro- gram) i cc5 fce f = v il , oe = v ih ?? 35 ma sram v cc active current i cc1 s v cc s = v cc s max., ce1 s = v il , ce2s = v ih t cycle = 10 mhz ?? 40 ma sram v cc active current i cc2 s ce1 s = 0.2 v, ce2s = v cc s - 0.2 v, t cycle = 10 mhz ?? 40 ma t cycle = 1 mhz ?? 8ma flash v cc standby current i sb1 f v cc f = v cc f max., ce f = v cc f 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v ? 15 m a flash v cc standby current (reset ) i sb2 f v cc f = v cc f max., reset = v ss 0.3 v wp /acc = v cc f 0.3 v ? 15 m a flash v cc current (automatic sleep mode)* 3 i sb3 f v cc f = v cc f max., ce f = v ss 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v v in = v cc f 0.3 v or v ss 0.3 v ? 15 m a sram v cc standby current i sb1 s ce1 s 3 v cc s - 0.2v, ce2s 3 v cc s - 0.2v ? 0.2 7 m a sram v cc standby current i sb2 sce2s 0.2v ? 0.2 7 m a
mb84vd2118xa- 85 /mb84vd2119xa- 85 27 (continued) *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remain stable for 150ns. *4: applicable for only v cc f applying. *5: embedded alogorithm (program or erase) is in progress. (@5mhz) *6: v cc indicates lower of v cc f or v cc s. parameter symbol test conditions value unit min. typ. max. input low level v il ?- 0.3 ? 0.5 v input high level v ih ? 2.4 ? v cc + 0.3 * 6 v voltage for sector protection, and temporary sector unprotection (reset ) * 4 v id ? 11.5 ? 12.5 v voltage for program acceleration (wp /acc) * 4 v acc ? 8.5 9.0 9.5 v output low voltage level v ol v cc f = v cc f min., v cc s = v cc s min., i ol = 1.0 ma ?? 0.4 v output high voltage level v oh v cc f = v cc f min., v cc s = v cc s min., i oh = - 0.5 ma 2.4 ?? v flash low v cc f lock-out voltage v lko ? 2.3 ? 2.5 v
mb84vd2118xa -85 /mb84vd2119xa -85 28 2. ac characteristics ? ce timing ? timing diagram for alternating sram to flash parameter symbol test setup value unit jedec standard min. ce recover time ? t ccr ? 0ns t ccr t ccr t ccr t ccr cef ce1s ce2s
mb84vd2118xa- 85 /mb84vd2119xa- 85 29 ? read only operations characteristics (flash) note : test conditions - output load : 1 ttl gate and 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v to 3.0 v timing measurement reference level input : 1.5 v output : 1.5 v parameter symbol test setup value (note) unit jedec standard min. max. read cycle time t avav t rc ? 85 ? ns address to output delay t avqv t acc ce f = v il oe = v il ? 85 ns chip enable to output delay t elqv t ce foe = v il ? 85 ns output enable to output delay t glqv t oe ?? 35 ns chip enable to output high-z t ehqz t df ?? 30 ns output enable to output high-z t ghqz t df ?? 30 ns output hold time from addresses, ce f or oe , whichever occurs first t axqx t oh ? 0 ? ns reset pin low to read mode ? t ready ?? 20 m s
mb84vd2118xa -85 /mb84vd2119xa -85 30 ? read cycle (flash) address cef oe we dq output valid address stable t rc t acc t oe t df t oeh t ce f high-z high-z address cef reset dq output valid address stable t rc t acc t rh t ce f t rh t rp t oh high-z
mb84vd2118xa- 85 /mb84vd2119xa- 85 31 ? erase/program operations (flash) (continued) parameter symbol value unit jedec standard min. typ. max. write cycle time t avav t wc 85 ?? ns address setup time (we to addr.) t avwl t as 0 ?? ns address setup time to ce f low during toggle bit polling ? t aso 15 ?? ns address hold time (we to addr.) t wlax t ah 45 ?? ns address hold time from ce f or oe high during toggle bit polling ? t aht 0 ?? ns data setup time t dvwh t ds 35 ?? ns data hold time t whdx t dh 0 ?? ns output enable setup time ? t oes 0 ?? ns output enable hold time read ? t oeh 0 ?? ns toggle and data polling 10 ?? ns ce f high during toggle bit polling ? t ceph 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? ns read recover time before write (oe to ce f) t ghel t ghel 0 ?? ns read recover time before write (oe to we ) t ghwl t ghwl 0 ?? ns we setup time (ce f to we ) t wlel t ws 0 ?? ns ce f setup time (we to ce f) t elwl t cs 0 ?? ns we hold time (ce f to we ) t ehwh t wh 0 ?? ns ce f hold time (we to ce f) t wheh t ch 0 ?? ns write pulse width t wlwh t wp 35 ?? ns ce f pulse width t eleh t cp 35 ?? ns write pulse width high t whwl t wph 30 ?? ns ce f pulse width high t ehel t cph 30 ?? ns byte programming operation t whwh1 t whwh1 ? 8 ?m s word programming operation ? 16 ?m s sector erase operation * 1 t whwh2 t whwh2 ? 1 ? s
mb84vd2118xa -85 /mb84vd2119xa -85 32 (continued) *1: this does not include the preprogramming time. *2: this timing is for sector protection operation. *3: the time between writes must be less than t tow otherwise that command will not be accepted and erasure will start. a time-out or t tow from the rising edge of last ce f or we whichever happens first will initiate the execution of the sector erase command (s) . *4: when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation. parameter symbol value unit jedec standard min. typ. max. v cc f setup time ? t vcs 50 ??m s voltage transition time * 2 ? t vlht 4 ??m s rise time to v id * 2 ? t vidr 500 ?? ns rise time to v acc ? t vaccr 500 ?? ns recover time from ry/by ? t rb 0 ?? ns reset pulse width ? t rp 500 ?? ns delay time from embedded output enable ? t eoe ?? 85 ns reset hold time before read ? t rh 200 ?? ns program/erase valid to ry/by delay ? t busy ?? 90 ns erase time-out time * 3 ? t tow 50 ??m s erase suspend transition time * 4 ? t spd ?? 20 m s
mb84vd2118xa- 85 /mb84vd2119xa- 85 33 ? write cycle (we control) (flash) address we oe cef dq 3rd bus cycle 555h a0h pd dq 7 d out d out pa pa data polling t wc t cs t wp t ds t dh t oh t oe t ce f t wph t whwh1 t ghwl t ch t as t ah t rc notes : 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mb84vd2118xa -85 /mb84vd2119xa -85 34 ? write cycle (ce f control) (flash) address we oe cef dq 3rd bus cycle 555h a0h pd dq 7 d out pa pa data polling t wc t ws t cp t ds t dh t cph t whwh1 t ghel t wh t as t ah notes : 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mb84vd2118xa- 85 /mb84vd2119xa- 85 35 ? ac waveforms chip/sector erase operations (flash) 555h 2aah 2aah 555h 555h t wc t ghwl t as t ah sa * address we oe cef dq v cc f t cs t ch t vcs t wph t wp t ds t dh aah 55h 80h aah 55h 10h/ 30h 30h for sector erase note : these waveforms are for the 16 mode. (the addresses differ from 8 mode.) *: sa is the sector address for sector erase. address = 555h for chip erase.
mb84vd2118xa -85 /mb84vd2119xa -85 36 ? ac waveforms for data polling during embedded algorithm operations (flash) we oe cef dq 7 dq (dq 0 to dq 6 ) ry/by data in data in dq 7 = valid data dq 0 to dq 6 valid data t eoe dq 7 dq 0 to dq 6 = output flag t ch t oe t df t oeh t ce f t whwh1 or 2 t busy high-z high-z * *: dq 7 = valid data (the device has completed the embedded operation.)
mb84vd2118xa- 85 /mb84vd2119xa- 85 37 ? ac waveforms for toggle bit during embedded algorithm operations (flash) address we cef oe dq 6 /dq 2 ry/by toggle data data toggle data toggle data stop toggling output valid t dh t oeh t oeph t busy t oe t ce f * t oeh t aht t ceph t as t aht t aso * : dq 6 stops toggling (the device has completed the embedded operation) .
mb84vd2118xa -85 /mb84vd2119xa -85 38 ? back-to-back read/write timing diagram (flash) address we oe cef dq valid output valid input (a0h) valid output valid output status valid input (pd) t rc t as t wc t rc t wc t rc t as t aht t ceph t rc read command read command read read ba1 ba2 (555h) ba2 (pa) ba2 (pa) ba1 ba1 t ah t ce f t oe t ghwl t oeh t df t df t wp t ds t dh t acc note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address of bank 1. ba2 : address of bank 2.
mb84vd2118xa- 85 /mb84vd2119xa- 85 39 ? ry/by timing diagram during write/erase operations (flash) ? reset , ry/by timing diagram (flash) the rising edge of the last write pulse entire programming or erase operations t busy ry/by we cef ry/by reset we t ready t rp t rb
mb84vd2118xa -85 /mb84vd2119xa -85 40 ? temporary sector unprotection (flash) ry/by reset v cc f 3 v 3 v cef we v id program or erase command sequence unprotection period t vcs t vidr t vlht t vlht t vlht
mb84vd2118xa- 85 /mb84vd2119xa- 85 41 ? extended sector protection (flash) v cc f reset address a 0 a 1 a 6 cef data 60h 60h 40h 01h 60h t vcs t vidr t vlht t wc t wc t wp time - out t oe sgax sgax sgay oe we sgax : sector group address to be protected sgay : next group sector address to be protected time-out : time-out window = 250 m s (min.)
mb84vd2118xa -85 /mb84vd2119xa -85 42 ? accelerated program (flash) 3 v wp/acc v cc f cef we ry/by t vlht program command sequence 3 v t vlht t vcs t vaccr v acc t vlht acceleration period
mb84vd2118xa- 85 /mb84vd2119xa- 85 43 ? read cycle (sram) note: test conditions: output load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to v cc s timing measurement reference level input: 0.5 v cc s output: 0.5 v cc s parameter symbol value unit min. max. read cycle time t rc 85 ? ns address access time t aa ? 85 ns chip enable (ce1 s) access time t co1 ? 85 ns chip enable (ce2s) access time t co2 ? 85 ns output enable access time t oe ? 45 ns lb s , ub s to output valid t ba ? 85 ns chip enable (ce1 s low and ce2s high) to output active t coe 5 ? ns output enable low to output active t oee 0 ? ns ub s , lb s enable low to output active t be 0 ? ns chip enable (ce1 s high or ce2s low) to output high-z t od ? 35 ns output enable high to output high-z t odo ? 35 ns ub s , lb s output enable to output high-z t bd ? 50 ns output data hold time t oh 10 ? ns
mb84vd2118xa -85 /mb84vd2119xa -85 44 ? read cycle ( note ) (sram) note : we remains h for the read cycle. address oe ce2s ce1s lb s , ub s dq t rc t oh t od t od t odo t bd t aa t co1 t co2 t oe t oee t ba t be t coe t coe valid data out
mb84vd2118xa- 85 /mb84vd2119xa- 85 45 ? write cycle (sram) parameter symbol value unit min. max. write cycle time t wc 85 ? ns write pulse width t wp 55 ? ns chip enable to end of write t cw 70 ? ns address valid to end of write t aw 70 ? ns ub s , lb s to end of write t bw 55 ? ns address setup time t as 0 ? ns write recovery time t wr 0 ? ns we low to output high-z t odw ? 35 ns we high to output active t oew 0 ? ns data setup time t ds 35 ? ns data hold time t dh 0 ? ns
mb84vd2118xa -85 /mb84vd2119xa -85 46 ? write cycle (note 3) (we control) (sram) t wc t as t wp t wr t aw t cw t cw t bw t odw t ds t dh t oew address we lb s , ub s ce1s ce2s d out d in note 1 note 2 note 4 note 4 valid data in notes : 1. if ce1 s goes l (or ce2s goes h) coincident with or after we goes l, the output will remain at high-z. 2. if ce1 s goes h (or ce2s goes l) coincident with or before we goes h, the output will remain at high-z. 3. if oe is h during the write cycle, the outputs will remain at high-z. 4. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied.
mb84vd2118xa- 85 /mb84vd2119xa- 85 47 ? write cycle (note 1) (ce1 s control) (sram) t wc t as t wp t wr t aw t cw t cw t bw t odw t ds t dh t coe t be valid data in address we lb s , ub s ce1s ce2s d out d in note 2 notes : 1. if oe is h during the write cycle, the outputs will remain at high-z. 2. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied.
mb84vd2118xa -85 /mb84vd2119xa -85 48 ? write cycle (note 1) (ce2s control) (sram) address we ce1s ce2s lb s , ub s d out d in note 2 valid data in t ds t odw t coe t be t bw t cw t cw t wp t wc t as t wr t aw t dh notes : 1. if oe is h during the write cycle, the outputs will remain at high-z. 2. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied.
mb84vd2118xa- 85 /mb84vd2119xa- 85 49 ? write cycle (note 1) (lb s, ub s control) (sram) address we ce1s ce2s d out d in lb s , ub s valid data in t ds t odw t coe t be t bw t as t aw t cw t cw t wp t wc t wr t dh note 2 notes : 1. if oe is h during the write cycle, the outputs will remain at high-z. 2. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied.
mb84vd2118xa -85 /mb84vd2119xa -85 50 n n n n erase and programming performance (flash) n n n n data retention characteristics (sram) * : 4 m a max. at t a 60 c, 1 m a max. at t a 40 c note : t rc : read cycle time ? ce1 s controlled data retention mode (note 1) parameter limits unit comment min. typ. max. sector erase time ? 110s excludes programming time prior to erasure byte programming time ? 8 300 m s excludes system-level overhead word programming time ? 16 360 m s excludes system-level overhead chip programming time ?? 50 s excludes system-level overhead erase/program cycle 100,000 ?? cycle parameter symbol value unit min. typ. max. data retention supply voltage v dh 1.5 ? 3.6 v standby current v dh = 3.0 v i dds2 ? 0.2 7* m a chip deselect to data retention mode time t cdr 0 ?? ns recovery time t r t rc ?? ns data retention mode see note 2 see note 2 t r t cdr v ccs - 0.2 v v cc s v ih v dh ce1s 2.7 v gnd
mb84vd2118xa- 85 /mb84vd2119xa- 85 51 ? ce2s controlled data retention mode (note 3) notes : 1. in ce1 s controlled data retention mode, input level of ce2s should be fixed vccs to vccs - 0.2 v or vss to 0.2 v during data retention mode. other input and input/output pins can be used between - 0.3 v and vccs + 0.3 v. 2. when ce1 s is operating at the v ih min. level (2.2 v) , the standby current is given by i sb1 s during the transition of v cc s from 3.6 to 2.2 v. 3. in ce2s controlled data retention mode, input and input/output pins can be used between - 0.3 v and vccs + 0.3 v. n n n n pin capacitance note : test conditions t a = 25 c, f = 1.0 mhz n n n n handling of package please handle this package carefully since the sides of packages are right angle. n n n n caution 1. the high voltage (v id ) can not apply to address pins and control pins except reset . therefore, it can not use autoselect and sector protect function by applying the high voltage (v id ) to specific pins. 2. for the sector protection, since the high voltage (v id ) can be applied to the reset , it can be protected the sector using extended sector protect command. parameter symbol test setup value unit typ. max. input capacitance c in v in = 01114pf output capacitance c out v out = 01216pf control pin capacitance c in2 v in = 01416pf wp /acc pin capacitance c in3 v in = 01720pf 0.2 v data retention mode v cc s ce2s v dh v ih v il t cdr t r gnd 2.7 v
mb84vd2118xa -85 /mb84vd2119xa -85 52 n n n n ordering information mb84vd2118 x a -85 -pbs device number/description 16mega-bit (2m 8-bit or 1m 16-bit) dual operation flash memory 3.0 v-only read, program, and erase 4mega-bit (512k 8-bit) sram boot code sector architecture 84vd2118 = top sector 84vd2119 = bottom sector pa c k a g e t y p e pbs = 69-ball fbga pts = 56-pin tsop (i) speed option see product selector guide. device revision bank size 1 = 0.5 mbit / 15.5 mbit 2 = 2 mbit / 14 mbit 3 = 4 mbit / 12 mbit 4 = 8 mbit / 8 mbit
mb84vd2118xa- 85 /mb84vd2119xa- 85 53 n n n n package dimensions (continued) 69-ball plastic fbga (bga-69p-m02) dimension in mm (inches) c 1999 fujitsu limited b69002s-1c-1 11.00?.10(.433?004) .049 ?004 +.006 ?.10 +0.15 1.25 (mounting height) 0.38?.10 (.015?004) (stand off) 1 2 3 4 5 6 7 8 9 10 a b c d e f g h 0.80(.031) 5.60(.220)ref 0.80(.031) 7.20(.283) ref 5.60(.220) index ball 69-0.18 ?002 +.004 ?.05 +0.10 69-0.45 m 0.08(.003) 0.10(.004) index-mark area 8.00?.10 (.315?004) 7.20(.283) j k
mb84vd2118xa -85 /mb84vd2119xa -85 54 (continued) 56-pin plastic tsop (i) (fpt-56p-m04) dimension in mm (inches) 0.145 +0.05 ?.03 +.002 ?001 .006 0?8 details of "a" part 0.25(.010) (.018/.030) 0.45/0.75 "a" 0.08(.003) (mounting height) (.045?002) 1.15?.05 (stand off) (.004?002) 0.10?.05 index 12.00?.10 (.472?004) 0.10(.004) m (.007?001) 0.18?.035 typ 0.40(.016) 14.00?.20(.551?008) 12.40?.10(.488?004) 1998 fujitsu limited f56004s-1c-1 c
m b84vd2118xa- 8 5 / m b84vd2119xa- 8 5 fujitsu limited f o r fur t her inf o r m ation please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://ede v ice . fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - f r i.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www . fujitsumicro . com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www . fujitsu-fme .com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www . fmap .com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f010 4 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB84VD21194A-85-PTS

	To Download MB84VD21194A-85-PTS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .